The CS4265 is a stereo audio codec featuring an integrated five-chip design and S/PDIF output to provide premium audio performance. An analog front-end provides a 2:1 input mux and a programmable gain amplifier (PGA) capable of ±12 dB of analog gain in 0.5 dB step sizes with zero-crossing and click-free transitions to maintain superior audio quality. One pair of inputs has a dedicated microphone pre-amplifier in its path to provide 32 dB of gain, and a low noise microphone bias supply is also available. The stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion is based on multibit Delta Sigma architecture. A synchronous S/PDIF (IEC60958-3) digital audio transmitter is integrated to provide additional design flexibility and to lower system cost.

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Technology

Mono/Stereo Codecs

Features

  • Complete stereo codec
  • Integrated 192 kHz S/PDIF transmitter
  • 24-bit conversion
  • System sampling rates up to 192 kHz
  • Advanced multibit Delta Sigma architecture
  • 104 dB dynamic range
  • -95 dB ADC THD+N
  • -90 dB DAC THD+N
  • 2:1 input mux
  • IEC60958-3 transmitter
  • Programmable gain amplifier: ±12 dB gain, 0.5 dB step sizes with zero crossing
  • Microphone pre-amp with 32 dB gain and low-noise bias supply
  • Digital volume control
  • Popguard® technology for control of clicks and pops
  • Single-ended inputs and outputs
  • 3.3 V or 5.0 V power supply
  • Support for direct interface to logic levels from 1.8 V to 5 V
  • Overflow detection
  • High-pass filter with defeat
  • Package: 32-pin QFN, lead-free assembly

Parametric Specifications

Channels In 2
Channels Out 2
DAC THD+N (dB) -90
ADC THD+N (dB) -95
Analog Power Supply (V) 3.3-5
Digital Power Supply (V) 3.3-5
Logic Power Supply (V) 1.8-5
Operational Power Consumption (mW) 198-400
Package 32 QFN

Technical Documents

CS4265 Product Data Sheet

Oct 1, 2021, DS658F6 : 2.3 Mb

CS4265 Product Bulletin

Jun 14, 2004, 0139-0604-PB-LP : 383 Kb

Errata: CS4265 Rev C0 Silicon

Jan 10, 2007, ER657F1 : 35 Kb

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Comprehensive Solutions