Fractional-N Clock Synthesizer and Multiplier
The CS2500 is a system-clocking device incorporating a programmable phase-locked loop (PLL). The hybrid analog/ digital PLL architecture comprises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL). The CS2500 enables frequency synthesis and clock generation from a stable timing reference clock. The device can generate low-jitter clocks from a noisy clock reference at frequencies as low as 150 Hz. The CS2500 can be configured using a control interface supporting I2C and SPI modes of operation.
The CS2500 can be powered from a single 1.8 V or 3.3 V supply. The device combines high performance with low power consumption.
The CS2500 is available in commercial-grade 10-pin TSSOP package for operation from –40°C to +85°C. The device is also available in the AEC-Q100-qualified grade-2 package for operation from –40°C to +105°C.
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Technology
Features
- High-performance analog/digital phase locked loop
- Clock frequency synthesizer incorporating delta-sigma fractional-N analog PLL
- Generates low-jitter 6–75 MHz clock (CLK_OUT) from 8–75 MHz timing reference (REF_CLK_IN)
- Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL
- Generates low-jitter 6–75 MHz clock (CLK_OUT), synchronized to a 150 Hz–30 MHz low-quality or intermittent frequency reference (CLK_IN)
- Flexible timing reference source
- External clock or external crystal
- Great performance
- High resolution PLL ratio (1 PPM)
- 18 psRMS period jitter
- Glitchless clock output generated from intermittent input
- I2C/SPI control port
- Configurable auxiliary clock/status output
- Minimal board space required
- No external analog loop-filter components
- Pin-to-pin, register map, and control compatible with CS2000 and CS2200
- Single-supply operation at 1.8 V or 3.3 V
Parametric Specifications
| Host Interface | true |
| One-Time-Programmable | false |
| Frequency Synth / Clock Generator | true |
| Clock Multiplier / Jitter Removal | true |
| Power Supply (V) |
1.8; 3.3 |
| Input Frequency Range | 150 Hz to 30 MHz |
| Reference Frequency Range (MHz) | 8-75 |
| Output Frequency Range (MHz) | 6-75 |
| Package | 10L-TSSOP |
Technical Documents
CDB2500-DC-SD Schematic Layout
558.9 KBCS2500 Product Data Sheet
Jan 1, 2026, DS1343F2 : 2.4 MBCDB-CLOCKING User Guide
Jun 1, 2024, DS1386DB1 : 2.7 MBCDB-CLOCKING-MB Schematic and Block Diagram
Jun 1, 2024, CDB-CLOCKING-MB-REV-B : 715KBCS2500 Migration Document
May 1, 2024, AN0630R1 : 137 KBCS2XXX Device ID Compatibility
Mar 1, 2024, AN0626R1 : 90 KBPress Releases
2024
Dec 05
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